Kontakt
Ako nakupovať
Doručenie
Nákupný poradca
Wire Aware Cache Architecture
Angličtina
145 b
30 dní na vrátenie tovaru
Zákazníci tiež kúpili
/
Brožovaná
35.74
€
/
Brožovaná
28.55
€
/
Brožovaná
57.91
€
Technology scaling has resulted in a steady increase in transistor speed. However, unlike transistors, global wires that span across the chip show a reverse trend of getting slower with shrinking process. Modern processors are severely constrained by wire delay and the widening gap between transistors and wires will only exacerbate the problem. Following the traditional design approach of adopting a single design point for all global wires will be suboptimal in terms of both power and performance. VLSI techniques allow several wire implementations with varying latency, power, and bandwidth properties. The dissertation advocates exposing wire properties to architects and demonstrates that prudent management of wires at the microarchitectural level can lead to significant improvement in power and delay characteristics of future communication bound processors. A heterogeneous interconnect (composed of wires with different latency, bandwidth, and power characteristics) is proposed that leverages varying latency and bandwidth needs of on-chip global messages to alleviate interconnect overhead.
Informácie o knihe
Angličtina
Darujte túto knihu ešte dnes
Je to jednoduché
1 Pridajte knihu do košíka a vyberte možnosť doručiť ako darček 2 Obratom Vám zašleme poukaz 3 Knihu zašleme na adresu obdarovanéhoMohlo by vás tiež zaujímať
/
Brožovaná
8.19
€
/
Pevná
45.46
€
Ahoj! Som Libroamiko, tvoj knižný radca.
Ako ti môžem pomôcť?