Nanoscale Strain-engineering in Solid State Semiconductor Devices

An analytical model has been developed that estimates induced stress in horizontally embedded nanowires. Stress has been considered to be induced due to mismatch of both lattice and thermo-elastic constants. The contribution of both process- and substrate-induced stress has been accounted for. Various materials have been chosen as substrate for different nanowire materials, depending on their crystal structures. The magnitude and nature of induced stress has been engineered by varying the fractional insertion of the nanowire into the substrate. Nanowires being extremely petite structures always need to be mounted on some substrate. Hence, a commercial substrate has been proposed, such that mobility enhancement through stress-engineering might be accomplished by varying the fractional insertion. Step-by-step stress-engineering for partially embedded nanowire FETs has been performed. The choice of high-k gate dielectric has been shown to play an important role. Similar stress-engineering has been performed for UTB MOSFETs and FinFETs. Both such FETs have been proposed to be fabricated on ingenious, commercial IOS substrates, capable of inducing stress of desired nature and magnitude.